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FauPU 10 Linux c++ 2015

Three layer hardware creation in a graphical editor

The hardware can be simulated and taped out onto a fpga to produce rapid results

CU Ebene

On the toplevel Computational Units are connected by a bus system and a shared Memory below.
Every CU can contain one or many PE Arrays.

PE Array

This is an array of processing elements that are aranged in 2 or 3 dimensional patterns.
Each element is connected to it's neighbours allowing for efficient data transfers with each cycle.

Within a PE

Within PEs the user can configure the calculations made with small graphical trees or by inserting the formular in the options menu.